This disclosure relates to integrated circuit devices, and more specifically, to a method and structure to create advanced metal conductor structures in semiconductor devices.
As the dimensions of modern integrated circuitry in semiconductor chips continues to shrink, conventional lithography is increasingly challenged to make smaller and smaller structures. With the reduced size of the integrated circuit, packaging the chips more closely together becomes important as well. By placing chips closer to each other, the performance of the overall computer system is improved.
It is typical to deposit a liner material prior to the deposition of a metal for forming a conductive line layer in semiconductor devices. In some applications, the liner material prevents the metal from diffusing into an underlying dielectric. However, as the dimensions of the features continue to shrink, the liner material takes up an increasing amount of the cross-section allocated to the conductive line. As the liner material is not as conductive as the metal, and conductivity at small cross-section dimensions is challenging, it would be advantageous to develop new technologies that reduce the effect of the liner material on conductivity.